Est. read time: 3 minutes | Last updated: June 21, 2024 by John Gentile


Contents

Overview

Tools

Xilinx Vivado

Tcl

All Vivado actions are really Tcl language commands, and can even be seen in the Tcl console window within the Vivado GUI; this is useful for creating Tcl scripts which can automate/replicate the associated Vivado actions.

For further reference, see UG835 Vivado Tcl Command Reference Guide.

Version Control

Vivado generates a lot of intermediate files, only some of which are required for version control. Some of these files have machine/instance specific metadata, which can cause problems when directly running on another machine. In general, the easiest and most robust method is to write TCL files describing the overall project settings and dependencies. In recent Vivado versions, this is simply done in the Vivado TCL console:

  • To save project/changes to TCL, > write_project_tcl <create_prj_name>.tcl
  • To create project from TCL, > source <create_prj_name>.tcl

For more info, see Xilinx AR 56421.

Vivado Tips & Tricks

  • Quickly find the expected Vivado version of a project file by doing $ cat project.xpr | grep 'Vivado v'
  • When packaging custom IP for usage in Block Design flow, you can add a custom logo picture to your block by adding it in the ‘Utility XIT/TTCL’ file group (UG1118 Vivado Creating and Packaging Custom IP).
  • When using debug ILAs, it’s helpful to use a dictionary sort on a glob/vector before assigning to an ILA probe, so it shows up properly in debug tools, like connect_debug_port ila1/probe0 [lsort -dictionary [get_nets {signal_name_*}]]
  • The SmartConnect AXI Interconnect IP block is now the default (and only in Versal) way to connect AXI memory-mapped IP blocks together using Xilinx IP. However, much of it’s operation relies on tight integration with the Vivado Block Design (BD) flow. When integrating in a mixed RTL + BD project, a BD which has an AXI SmartConnect S-AXI or M-AXI interface go “external” (e.g. ports which are existent in the HDL wrapper of a BD) defaults to AXI4-Full. However, there are instances where you’d like that external port to utilize AXI4-Lite, such as when tying together that BD with an RTL block which uses AXI4-Lite in a top-level HDL file. The non-obvious way to change this is to first make your AXI ports to/from the SmartConnect in your BD, then change the external port (e.x. a port named m_axi) type to AXI-Lite with the Tcl command set_property CONFIG.PROTOCOL AXI4LITE [get_bd_intf_ports /m_axi]. Now when you save & validate your BD (e.g. save_bd_design; validate_bd_design; save_bd_design), the SmartConnect will know that these ports are AXI4-Lite and the BD’s HDL wrapper will have the proper signaling present.
  • Certain Vivado messages can have their severity level (e.g. Info, Warnings, Critical Warnings, Errors) changed to another severity level; for instance, to promote the “no clocks found” timing constraint Warning to an Error (to catch timing constraints that aren’t hitting):
    set_msg_config -id {Vivado 12-1008} -new_severity {ERROR}
    
Synthesis
  • Disabling LUT combining (-no_lc) or other resource sharing (-resource_sharing off) can be useful for highly congested designs as logic is not compressed into resources used by other logic; the trade is of course that you have higher LUT/resource utilization when disabling these features.

HW Debug

General Tips & Tricks

  • PCS loopback can hide GT RefClk issues (wrong frequency causing non-standard line rates for instance)

References

Conferences